The present invention relates generally to integrated circuit memory devices and, more particularly, to a method and system for using split voltage level restore and evaluate clock signals for memory address decoding.
As integrated memory circuits are scaled down it becomes desirable to reduce the power supply voltage. However, the individual memory cells (e.g., static random access memory or SRAM cells) are very sensitive to reductions in the applied voltage. As the supply voltage is reduced, there is an increase in memory write and read errors due to, for example, ambiguities in the value of a charge stored by the memory cell (e.g., soft errors). To reduce power consumption and enable further reduction in circuit size, one approach is to provide a reduced voltage level supply to circuits other than the memory cell array (e.g., decoders, clock circuits, etc.) while maintaining the voltage supplied to the memory cells at some desirable level. Even though the memory cells continue to be operated at the higher voltage and power levels, the net effect is to substantially reduce power consumption. Although the support circuits are continually operating, only a small number of the memory cells (e.g., only those actually being accessed) are fully powered at any particular time.
Implementing a sufficiently high voltage within a memory cell array while using a reduced voltage for other memory structures and interfacing devices may be accomplished by the use of level shifters to interface the components. For example, a “high” voltage supply with a low logic level of 0 volts (V) and a high logic level of 1.3 V may be used within a memory cell array while a high logic level of only 0.7 V may be used outside the array for other memory structures (e.g., support circuitry associated with the memory cell array such as address decoders and timing circuits) and interfacing devices (e.g., address and data busses). A transition from the lower voltage logic level to the higher voltage logic levels may be accomplished using such level shifters. While reducing power requirements, incorporating these level shifters consumes additional energy to power the level shifters and requires additional area or space on a chip. The level shifters may also introduce a delay in signal propagation time, skewing clock, control and data signals. Thus, the number and configuration of level shifters can affect memory size, timing and power requirements.
Accordingly, one challenge in designing dual voltage supply memory arrays is the consideration of how and when to transition from the low voltage supply, primarily used for powering peripheral circuits, to the high voltage supply that powers the memory cells. The point in the design chosen for such level shifting may have area implications; for example, the level shift may occur in a circuit stage that has repeated instances. Alternatively, there may be a latency impact if a level shift stage is introduced in a critical path solely for the purpose of translating the signal to the higher voltage supply.
In addition, there are also voltage differential (Vdiff) considerations for knowing how circuits powered by different supplies will behave as the supply steers away from nominal operating conditions. One conventional approach in this regard for memory applications is to delay introduction of the higher voltage to the final word decode stage. This has two disadvantages: first, this technique requires that each word decoder be an explicit level shifter, which increases the area. Second, while a simple “brute force” level shifter may be used to minimize area, such a level shift circuit does not support large Vdiff requirements. Still another alternative may be to level shift each input to the decoder. However, this approach would add stages of delay in the access path, which would in turn increase the setup time.